A memory cell, comprised of a number of transistors, operates by holding a voltage value over a period of time. This value translates to either a “1” (high voltage) or a “0” (low voltage) during a read operation of the memory. Constant voltage stress can lead to rapid degeneration of transistor parameters, such as threshold voltage and source-drain current. These effects are known as bias temperature instability (BTI) and become more pronounced and destructive as device sizes are reduced. BTI can be either negative BTI (NBTI) when the bias voltage is negative on a metal-oxide-semiconductor (MOS) structure or positive BTI (PBTI) when the bias voltage is positive. The NBTI effect is more severe for P-channel MOS (PMOS) transistors and the PBTI effect is more severe for N-channel MOS (NMOS) transistors. BTI degrades the reliability of MOS transistors due to the change in threshold voltage, and the degradation increases at elevated temperatures. However, if the stress is periodically interrupted or reversed, the degradation may be significantly reduced, extending the projected life time of the MOS transistors.
A conventional six-transistor static random access memory (SRAM) cell consists of two PMOS transistors and four NMOS transistors. With any data storage in the SRAM cell, the effects of NBTI degrade one of the PMOS transistors and the effects of PBTI degrade one of the NMOS transistors. If the same data is stored in the SRAM memory cell for an extended period of time, then there can be substantial degradation on the PMOS transistor and the NMOS transistor. During the operation of the SRAM, even if the data read and write operations are performed frequently with different data contents, there is a good possibility that some of the SRAM memory cells store the same high state or low state for an extended period of time. Again, these non-refreshed memory cells can have higher degradation in one of the PMOS transistors and one of the NMOS transistors which can decrease the reliability of the SRAM cell, as well as the life-time of the entire SRAM memory.
To combat these effects, a recovery period where the polarity of the memory cell is reversed (and hence the biases in the transistors) can be successful. Current strategies to reverse the polarity include the use of at least one inverter and data drivers to re-write the opposite values to the memory cell.